Philip E. Garrou, Ph.D.

Microelectronic Consultants of North Carolina

Research Triangle Park NC

Dr. Philip Garrou consults in the areas of thin film microelectronics, IC packaging and materials for microelectronics for startups and fortune 500 companies.

From 2002 – 2004 he was Global Director of Technology and New Business Development for Dow Chemicals Advanced Electronic Materials business. From 1997 – 2002 he was General Manager of Dows BCB polymer dielectric business. Dr. Garrou is a fellow of both IEEE & IMAPS and has served as President of the IEEE Components, Packaging and Manufacturing Technology Society ,CPMT (2003-2005) and IMAPS (1998)

Dr. Garrou was been Associate Editor of IEEE Transactions on Components and Packaging. He is currently editorial advisor and blogger (“Perspectives from the Leading Edge”) for Semiconductor International. He has authored three microelectronic texts and has co-authored over 100 book chapters and peer reviewed publications. His latest text is entitled “Handbook of 3D IC Integration: Technology and Applications”.

In 1994 he won the Milton Kiver Award for Excellence in Electronic Packaging and Production for the commercial introduction of CycloteneÔ Advanced Electronics Resins. In 2000 he won the IMAPS William Ashman award for “…technical achievement in Microelectronics Packaging”. In 2002 he won the Fraunhofer IZM International Advanced Packaging Award for “…pioneering achievement in the introduction of new thin film polymeric packaging materials.” In 2007 he won the IEEE CPMT Sustained Technical Achievement Award for “..for 25 years of technical contributions and leadership in thin film polymer dielectric materials and microelectronic applications including multichip modules, bumping and wafer level packaging, integrated passives, oLEDs and 3D integration”

Dr. Garrou received his B.S. degree in chemistry from North Carolina State University in 1970 and his PhD degree in chemistry from Indiana University in 1974.

Abstract: 3D IC Integration - An Emerging System Level Integration Architecture

This talk will begin by defining some of the terminology within 3D Integration and 3D Packaging, including such popular terms as “via first”, “via last”, and “through-silicon vias”. Market drivers for the surge in 3D interest will be explored, as well as some of the typical process sequences to create these highly integrated systems and packages. Within the various process schemes, such unit process steps as TSV etching, wafer thinning and bonding will be explored, examining some of the process details being proposed in various commercial, academic or institutional environments. Some specific applications being targeted for 3D Integration and Packaging will then be described, including memory devices, pairing of memory and logic, CMOS image sensors and ultimately, true heterogeneous integration. Finally, the author will look at some of the technical and market challenges for this novel technology to overcome in order to be completely successful.

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