Dallas, TX - May 14th, 2008

Venue: Embassy Suites Galleria
14021 Noel Road, Dallas, Texas, United States 75240
Tel: 972-364-3640

Agenda

Please click on the speakers names for bios and abstracts.

9:30 Registration
10:00 3D IC Integration, An Emerging System Level Integration Architecture Phil Garrou
MCNC
10:30 Advances in DRIE Technology for 200mm and 300mm Wafer Through Silicon Via (TSV) Applications Steve Vargo
STS
11:00 Development of 3D High-Performance Memory Bob Patti
Tezzaron
11:30 Electrochemical Copper Filling of High Aspect Ratio Through Silicon Vias Arthur Keigler
NEXX SYSTEMS
12:00 Lunch Break
13:00 Issues and Solutions to enable 3D Integration and Packaging Kathy Cook
SUSS MicroTec
13:30 Through Silicon Via: Fast Fill Chemistry Dr. Yun Zhang
Enthone
14:00 Material Solutions for 3D and TSV’s Chris Milasincic
DuPont
14:30 New Materials for 3D Integration Bob Forman
Rohm and Haas
15:00 Coffee Break
15:30 Thick Chemically-Amplified Photoresists for 3D TSV’s and Plating Aldo Orsi
AZ
16:00 KMPR - High-resolution DRIE and ultra-high aspect ratio plating resist for TSV and 3D packaging Harris Miller
MicroChem
16:30 Closing Remarks, Drawing, Password for presentations

The seminars will be held from 10:00AM – 5:00PM. Lunch and refreshments will be provided.

Please register here. We look forward to seeing you there.