Arthur Keigler

Vice President of Technology, NEXX Systems Inc.

Arthur has over 20 years experience in wafer processing. He holds an MS in materials science and engineering from MIT and a BS in applied and engineering physics from Cornell. He was also a Leaders for Manufacturing Fellow at MIT, earning an MS in business management and an MS in mechanical engineering. He holds several patents in the field of wafer processing equipment.

Abstract: Electrochemical Copper Filling of High Aspect Ratio Through Silicon Vias

A critical enabling technology for through silicon vias is the electrochemical deposition copper filling step. Void-free filling is required for high yield implementation of 3-D. Bottom-up filling of vias is necessary to prevent void formation. Optimization of the bottom-up via filling process will be discussed for vias ranging in diameter from 5 to 25 microns, with depths of 70 – 150 microns. The via filling time increases with both via diameter and via depth. By plating 20 wafers in parallel, through-silicon-via filling for 3D applications can be made economical. Process throughputs and corresponding cost model data for optimized via filling processes will be discussed.

Hosted by